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MIC4103/4104
100V Half Bridge MOSFET Drivers 3/2A Sinking/Sourcing Current PRELIMINARY
General Description
The MIC4103 and MIC4104 are high frequency, 100V Half Bridge MOSFET drivers with faster turn-off characteristics than the MIC4100 and MIC4101 drivers. They feature fast 24ns propagation delay times and 6ns driver fall times. The low-side and high-side gate drivers are independently controlled and matched to within 3ns typical. The MIC4103 has CMOS input thresholds and the MIC4104 has TTL input thresholds. The MIC4103/4 include a high voltage internal diode that charges the high-side gate drive bootstrap capacitor. A robust, high-speed, and low power level shifter provides clean level transitions to the high side output. The robust operation of the MIC4103/4 ensures the outputs are not affected by supply glitches, HS ringing below ground, or HS slewing with high speed voltage transitions. Undervoltage protection is provided on both the low-side and high-side drivers. The MIC4103 and MIC4104 are available in an 8-pin SOIC and 8-pin 3mm x 3mm MLF(R) package with a operating junction temperature range of -40C to +125C. Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Features
* Asymmetrical, low impedance outputs drive 1000pF load with 10ns rise times and 6ns fall times * Bootstrap supply max voltage to 118V DC * Supply voltage up to 16V * Drives high- and low-side N-Channel MOSFETs with independent inputs * CMOS input thresholds (MIC4103) * TTL input thresholds (MIC4104) * On-chip bootstrap diode * Fast 24ns propagation times * Low power consumption * Supply under-voltage protection * Typical 2.5 pull up and 1.25 pull down output driver resistance * -40C to +125C junction temperature range
Applications
* High voltage buck converters * Full- and half-bridge power topologies * Active clamp forward converter * Two switch forward topologies * Interface to digital controllers ___________________________________________________________________________________________________________
Typical Application
100V Buck Regulator Solution
MLF and MicroLead Frame is a registered trademark of Amkor Technologies, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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Ordering Information
Part Number MIC4103YM MIC4104YM MIC4103YML (coming soon) MIC4104YML (coming soon) Input CMOS TTL CMOS TTL Junction Temp. Range -40 to +125C -40 to +125C -40 to +125C -40 to +125C Package 8-Pin SOIC 8-Pin SOIC 8-Pin 3x3 MLF(R) 8-Pin 3x3 MLF(R)
Pin Configuration
8-Pin SOIC (M)
8-Pin 3mm x 3mm MLF(R) (ML)
Pin Description
Pin Number 1 2 3 4 5 6 7 8 Pin Name VDD HB HO HS HI LI VSS LO Pin Function Positive Supply to lower gate drivers. Decouple this pin to VSS (Pin 7). Bootstrap diode connected to HB (pin 2). High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-Side Output. Connect to gate of High-Side power MOSFET. High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-Side input. Low-Side input. Chip negative supply, generally will be ground. Low-Side Output. Connect to gate of Low-Side power MOSFET.
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Absolute Maximum Ratings(1)
Supply Voltage (VDD, VHB - VHS) ...................... -0.3V to 18V Input Voltages (VLI, VHI) ......................... -0.3V to VDD + 0.3V Voltage on LO (VLO) .............................. -0.3V to VDD + 0.3V Voltage on HO (VHO) ......................VHS - 0.3V to VHB + 0.3V Voltage on HS (continuous) .............................. -1V to 110V Voltage on HB ..............................................................118V Average Current in VDD to HB Diode.......................100mA Junction Temperature (TJ) ........................-55C to +150C Storage Temperature (Ts) ..........................-60C to +150C ESD Rating..........................................................See note 3
Operating Ratings(2)
Supply Voltage (VDD)........................................ +9V to +16V Voltage on HS ................................................... -1V to 100V Voltage on HS (repetitive transient) .................. -5V to 105V HS Slew Rate............................................................ 50V/ns Voltage on HB ...................................VHS + 8V to VHS + 16V and............................................ VDD - 1V to VDD + 100V Junction Temperature (TJ) ........................ -40C to +125C Junction Thermal Resistance SOIC-8L (JA)...................................................140C/W 3mm x 3mm MLF(R) ............................................tbdC/W
Electrical Characteristics(4)
VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = 25C; unless noted. Bold values indicate -40C< TJ < +125C. Symbol Parameter Condition Min Typ 40 3.0 25 1.5 0.05 Max 150 200 4.0 150 200 2.5 3 1 30 Units Supply Current IDD IDDO IHB IHBO IHBS VDD Quiescent Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent LI = HI = 0V f = 500kHz LI = HI = 0V f = 500kHz VHS = VHB = 110V A mA A mA A
Input Pins: MIC4103 (CMOS Input ) VIL VIH VIHYS RI Low Level Input Voltage Threshold High Level Input Voltage Threshold Input Voltage Hysteresis Input Pulldown Resistance Low Level Input Voltage Threshold High Level Input Voltage Threshold Input Pulldown Resistance VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis 6.0 100 6.5 100 4 3 5.3 5.7 0.4 200 500 7 8 V V V k
Input Pins: MIC4104 (TTL Input ) VIL VIH RI VDDR VDDH VHBR VHBH 0.8 1.5 1.5 200 7.4 0.5 7.0 0.4 8.0 2.2 500 8.0 V V k V V V V
Under Voltage Protection
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Symbol
Parameter
Condition
Min
Typ 0.4 0.7 1.0
Max 0.55 0.70 0.8 1.0 1.5 2.0 0.3 0.4 0.3 0.45
Units
Bootstrap Diode VDL VDH RD Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance IVDD-HB = 100A IVDD-HB = 100mA IVDD-HB = 100mA V V
LO Gate Driver VOLL VOHL IOHL IOLL Low Level Output Voltage High Level Output Voltage Peak Sink Current Peak Source Current ILO = 160mA ILO = -100mA, VOHL = VDD - VLO VLO = 0V VLO = 12V 0.18 0.25 3 2 0.22 0.25 3 2 0.3 0.4 0.3 0.45 V V A A
HO Gate Driver VOLH VOHH IOHH IOLH Low Level Output Voltage High Level Output Voltage Peak Sink Current Peak Source Current Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Lower Turn-On and Upper Turn-Off Delay Matching: Lower Turn-Off and Upper Turn-On Output Rise Time Output Fall Time CL = 1000pF CL = 1000pF IHO = 160mA IHO = -100mA, VOHH = VHB - VHO VHO = 0V VHO = 12V V V A A
Switching Specifications tLPHL tHPHL tLPLH tHPLH tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC tFC (MIC4103) (MIC4103) (MIC4103) (MIC4103) (MIC4104) (MIC4104) (MIC4104) (MIC4104) 24 24 24 24 24 24 24 24 3 3 10 6 45 45 45 45 45 45 45 45 8 10 8 10 ns ns ns ns ns ns ns ns ns ns ns ns
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Symbol
Parameter
Condition
Min
Typ 0.4 0.2
Max 0.6 0.8 0.3 0.4 50
Units
Switching Specifications (cont.) tR tF tPW tBS
Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. 4. Specification for packaged product only. 5. All voltages relative to pin 7, VSS unless otherwise specified 6. Guaranteed by design. Not production tested.
Output Rise Time (3V to 9V) Output Fall Time (3V to 9V) Minimum Input Pulse Width that Changes the Output Bootstrap Diode Turn-On or Turn-Off Time
CL = 0.1F CL = 0.1F Note 6
s s ns ns
10
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Timing Diagrams
Note: All propagation delays are measured from the 50% voltage level.
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Typical Characteristics
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Typical Characteristics
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Functional Characteristics
Figure 1. MIC4103/4 Functional Block Diagram
Functional Description
The MIC4103 is a high voltage, non-inverting, dual MOSFET driver that is designed to independently drive both high-side and low-side N-Channel MOSFETs. The block diagram of the MIC4103 is shown in Figure 1. Both drivers contain an input buffer with hysteresis, a UVLO circuit and an output buffer. The high-side output buffer includes a high speed level-shifting circuit that is referenced to the HS pin. An internal diode is used as part of a bootstrap circuit to provide the drive voltage for the high-side output. Startup and UVLO The UVLO circuit forces the driver output low until the supply voltage exceeds the UVLO threshold. The low-side UVLO circuit, monitors the voltage between the VDD and VSS pins. The high-side UVLO circuit monitors the voltage between the HB and HS pins. Hysteresis in the UVLO circuit prevents noise and finite circuit impedance from causing chatter during turn-on. Input Stage The MIC4103 and MIC4104 have different input stages, which lets these parts cover a wide range of driver applications. Both the HI and LI pins are referenced to the VSS pin. The MIC4103 has a high impedance, CMOS compatible input threshold and is recommended for applications October 2007 9
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where the input signal is noisy or where the input signal swings the full range of voltage (from VDD to GND). There is typically 400mV of hysteresis on the input pins throughout the VDD range. The hysteresis improves noise immunity and prevents input signals with slow rise times from falsely triggering the output. The threshold voltage of the MIC4103 varies proportionally with the VDD supply voltage. The amplitude of the input signal affects the VDD supply current. Vin voltages that are a diode drop less than the VDD supply voltage will cause an increase in the VDD pin current. The graph in Figure 2 shows the typical dependence between IVDD and Vin for Vdd=12V.
Micrel Figure 2. MIC4103 Supply Current vs. Input Voltage
MIC4103/4104
The MIC4104 has a TTL compatible input range and is recommended for use with inputs signals whose amplitude is less than the supply voltage. The threshold level is independent of the VDD supply voltage and there is no dependence between IVDD and the input signal amplitude with the MIC4104. This feature makes the MIC4104 an excellent level translator that will drive high threshold MOSFETs from a low voltage PWM IC. Low-Side Driver A block diagram of the low-side driver is shown in Figure 3. The low-side driver is designed to drive a ground (VSS pin) referenced N-channel MOSFET. Low driver impedances allow the external MOSFET to be turned on and off quickly. The rail-to-rail drive capability of the output ensures full enhancement of the external MOSFET. A high level applied to LI pin causes the upper driver FET to turn on and VDD voltage is applied to the gate of the external MOSFET. A low level on the LI pin turns off the upper driver and turns on the low side driver to ground the gate of the external MOSFET.
Vdd
Figure 4. High-Side Driver and Bootstrap Circuit Block Diagram A low power, high speed, level shifting circuit isolates the low side (VSS pin) referenced circuitry from the high-side (HS pin) referenced driver. Power to the high-side driver and UVLO circuit is supplied by the bootstrap circuit while the voltage level of the HS pin is shifted high. The bootstrap circuit consists of an internal diode and external capacitor, CB. In a typical application, such as the synchronous buck converter shown in Figure 5, the HS pin is at ground potential while the low-side MOSFET is on. The internal diode allows capacitor CB to charge up to VDD-VD during this time (where VD is the forward voltage drop of the internal diode). After the low-side MOSFET is turned off and the HO pin turns on, the voltage across capacitor CB is applied to the gate of the upper external MOSFET. As the upper MOSFET turns on, voltage on the HS pin rises with the source of the high-side MOSFET until it reaches VIN. As the HS and HB pin rise, the internal diode is reverse biased preventing capacitor CB from discharging.
CB Vin
LO
External FET
Vss
Figure 3. Low-Side Driver Block Diagram
CVDD HI
Vdd
Level shift
HB Q1 HO Lout
High-Side Driver and Bootstrap Circuit A block diagram of the high-side driver and bootstrap circuit is shown in Figure 4. This driver is designed to drive a floating N-channel MOSFET, whose source terminal is referenced to the HS pin.
HS LI LO
Q2
Vss
Figure 5. High-Side Driver and Bootstrap Circuit October 2007 10
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Application Information
Power Dissipation Considerations Power dissipation in the driver can be separated into three areas: * * * Internal diode dissipation in the bootstrap circuit Internal driver dissipation Quiescent current dissipation used to supply the internal logic and control functions.
The total diode power dissipation is: Pdiode total = Pdiode fwd + Pdiode RR An optional external bootstrap diode may be used instead of the internal diode (Figure 6). An external diode may be useful if high gate charge MOSFETs are being driven and the power dissipation of the internal diode is contributing to excessive die temperatures. The voltage drop of the external diode must be less than the internal diode for this option to work. The reverse voltage across the diode will be equal to the input voltage minus the VDD supply voltage. A 100V Schottky diode will work for most 72Vinput telecom applications. The above equations can be used to calculate power dissipation in the external diode, however, if the external diode has significant reverse leakage current, the power dissipated in that diode due to reverse leakage can be calculated as:
Bootstrap Circuit Power Dissipation Power dissipation of the internal bootstrap diode primarily comes from the average charging current of the CB capacitor times the forward voltage drop of the diode. Secondary sources of diode power dissipation are the reverse leakage current and reverse recovery effects of the diode. The average current drawn by repeated charging of the high-side MOSFET is calculated by:
I F ( AVE ) = Qgate x fS where : Q gate = Total Gate Charge at VHB fS = gate drive switching frequency The average power dissipated by the forward voltage drop of the diode equals:
Pdiode fwd = I F ( AVE ) x VF where : VF = Diode forward voltage drop The value of VF should be taken at the peak current through the diode, however, this current is difficult to calculate because of differences in source impedances. The peak current can either be measured or the value of VF at the average current can be used and will yield a good approximation of diode power dissipation. The reverse leakage current of the internal bootstrap diode is typically 11A at a reverse voltage of 100V and 125C. Power dissipation due to reverse leakage is typically much less than 1mW and can be ignored. Reverse recovery time is the time required for the injected minority carriers to be swept away from the depletion region during turn-off of the diode. Power dissipation due to reverse recovery can be calculated by computing the average reverse current due to reverse recovery charge times the reverse voltage across the diode. The average reverse current and power dissipation due to reverse recovery can be estimated by:
I RR ( AVE ) = 0.5 x I RRM x t rr x fS Pdiode RR = I RR ( AVE ) x VREV where : IRRM = Peak Reverse Recovery Current t rr = Reverse Recovery Time
Pdiode REV = I R x VREV x (1 - D ) where : IR = Reverse current flow at VREV and TJ VREV = Diode Reverse Voltage D = Duty Cycle = t ON / fS fs = switching frequency of the power supply The on-time is the time the high-side switch is conducting. In most power supply topologies, the diode is reverse biased during the switching cycle off-time.
CB Vdd HI
Level shift
Vin
HB
HO HS
LI
LO
Vss
Figure 6. Optional Bootstrap Diode
Gate Driver Power Dissipation Power dissipation in the output driver stage is mainly caused by charging and discharging the gate to source 11
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Micrel and gate to drain capacitance of the external MOSFET. Figure 7 shows a simplified equivalent circuit of the MIC4103 driving an external MOSFET.
MIC4103/4104
Vdd
HB
External FET
Ron CB HO Rg Roff
Cgd
Rg_fet Cgs
HS
Figure 8. Typical Gate Charge vs. VGS
The same energy is dissipated by ROFF, RG, and RG_FET when the driver IC turns the MOSFET off. Assuming RON is approximately equal to Roff, the total energy and power dissipated by the resistive drive elements is:
Edriver = QG x VGS and Pdriver = QG x VGS x fs where Edriver is the energy dissipated per switching cycle Pdriver is the power dissipated by switching the MOSFET on and off QG is the total gate charge at Vgs VGS is the gate to source voltage on the MOSFET fs is the switching frequency of the gate drive circuit
Figure 7. MIC4103 Driving an External MOSFET
Dissipation during the external MOSFET Turn-On Energy from capacitor CB is used to charge up the input capacitance of the MOSFET (CGD and CGS). The energy delivered to the MOSFET is dissipated in the three resistive components, RON, RG, and RG_FET. RON is the on resistance of the upper driver MOSFET in the MIC4103. RG is the series resistor (if any) between the driver IC and the MOSFET. RG_FET is the gate resistance of the MOSFET. RG_FET is usually listed in the power MOSFET's specifications. The ESR of capacitor CB and the resistance of the connecting trace can be ignored since they are much less than RON and RG_FET. The effective capacitance of CGD and CGS is difficult to calculate since they vary non-linearly with ID, VGS, and VDS. Fortunately, most power MOSFET specifications include a typical graph of total gate charge vs. VGS. Figure 8 shows a typical gate charge curve for an arbitrary power MOSFET. This chart shows that for a gate voltage of 10V, the MOSFET requires about 23.5nC of charge. The energy dissipated by the resistive components of the gate drive circuit during turn-on is calculated as:
E= but Q = Cx V so E = 1/2 x Qg x Vgs where Ciss is the total gate capacitance of the MOSFET
1 2
The power dissipated inside the MIC4103/4 is equal to the ratio of RON & ROFF to the external resistive losses in RG and RG_FET. Letting RON =ROFF, the power dissipated in the MIC4103 due to driving the external MOSFET is:
Pdiss drive = Pdriver
RON
RON + RG + RG _ FET
x Ciss x Vgs 2
Supply Current Power Dissipation Power is dissipated in the MIC4103 even if there is nothing being driven. The supply current is drawn by the bias for the internal circuitry, the level shifting circuitry, and shootthrough current in the output drivers. The supply current is proportional to operating frequency and the VDD and VHB voltages. The typical characteristic graphs show how supply current varies with switching frequency and supply voltage.
The power dissipated by the MIC4103 due to supply current is:
Pdiss sup ply = VDD x I DD + VHB x I HB
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MIC4103/4104 must be allowed for the CB capacitor to charge up before the high-side driver is turned on.
Total power dissipation and Thermal Considerations Total power dissipation in the MIC4103 or MIC4104 is equal to the power dissipation caused by driving the external MOSFETs, the supply current, and the internal bootstrap diode.
Pdiss total = Pdiss supply + Pdiss drive + Pdiode total
The die temperature may be calculated once the total power dissipation is known.
TJ = T A + Pdiss total x JA
where : TA is the maximum ambient temperature TJ is the junction temperature (C) Pdisstotal is the power dissipation of the MIC4103/4 JC is the thermal resistance from junction to ambient air (C/W)
Propagation Delay and Delay Matching and other Timing Considerations Propagation delay and signal timing is an important consideration in a high performance power supply. The MIC4103 is designed not only to minimize propagation delay but to minimize the mismatch in delay between the high-side and low-side drivers.
Fast propagation delay between the input and output drive waveform is desirable. It improves overcurrent protection by decreasing the response time between the control signal and the MOSFET gate drive. Minimizing propagation delay also minimizes phase shift errors in power supplies with wide bandwidth control loops. Many power supply topologies use two switching MOSFETs operating 180 out of phase from each other. These MOSFETs must not be on at the same time or a short circuit will occur, causing high peak currents and higher power dissipation in the MOSFETs. The MIC4103 and MIC4104 output gate drivers are not designed with anti-shoot-through protection circuitry. The output drive signals simply follow the inputs. The power supply design must include timing delays (dead-time) between the input signals to prevent shoot-through. The MIC4103 & MIC4104 drivers specify delay matching between the two drivers to help improve power supply performance by reducing the amount of dead-time required between the input signals. Care must be taken to insure the input signal pulse width is greater than the minimum specified pulse width. An input signal that is less than the minimum pulse width may result in no output pulse or an output pulse whose width is significantly less than the input. The maximum duty cycle (ratio of high side on-time to switching period) is controlled by the minimum pulse width of the low side and by the time required for the CB capacitor to charge during the off-time. Adequate time October 2007 13
Decoupling and Bootstrap Capacitor Selection Decoupling capacitors are required for both the low side (Vdd) and high side (HB) supply pins. These capacitors supply the charge necessary to drive the external MOSFETs as well as minimize the voltage ripple on these pins. The capacitor from HB to HS serves double duty by providing decoupling for the high-side circuitry as well as providing current to the high-side circuit while the high-side external MOSFET is on. Ceramic capacitors are recommended because of their low impedance and small size. Z5U type ceramic capacitor dielectrics are not recommended due to the large change in capacitance over temperature and voltage. A minimum value of 0.1uf is required for each of the capacitors, regardless of the MOSFETs being driven. Larger MOSFETs may require larger capacitance values for proper operation. The voltage rating of the capacitors depends on the supply voltage, ambient temperature, and the voltage derating used for reliability. 25V rated X5R or X7R ceramic capacitors are recommended for most applications. The minimum capacitance value should be increased if low voltage capacitors are used since even good quality dielectric capacitors, such as X5R, will lose 40% to 70% of their capacitance value at the rated voltage.
Placement of the decoupling capacitors is critical. The bypass capacitor for Vdd should be placed as close as possible between the Vdd and Vss pins. The bootstrap capacitor (CB) for the HB supply pin must be located as close as possible between the HB and HS pins. The trace connections must be short, wide, and direct. The use of a ground plane to minimize connection impedance is recommended. Refer to the section on layout and component placement for more information. The voltage on the bootstrap capacitor drops each time it delivers charge to turn on the MOSFET. The voltage drop depends on the gate charge required by the MOSFET. Most MOSFET specifications specify gate charge vs. Vgs voltage. Based on this information and a recommended VHB of less than 0.1V, the minimum value of bootstrap capacitance is calculated as:
CB
Qgate VHB
where : Q gate = Total Gate Charge at VHB HB = Voltage drop at the HB pin The decoupling capacitor for the Vdd input may be calculated with the same formula, however, the two capacitors are usually equal in value.
Grounding, Component Placement, and Circuit Layout Nanosecond switching speeds and ampere peak currents
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Micrel in and around the MIC4103 and MIC4104 drivers require proper placement and trace routing of all components. Improper placement may cause degraded noise immunity, false switching, excessive ringing or circuit latch-up. Figure 9 shows the critical current paths when the driver outputs go high and turn on the external MOSFETs. It also helps demonstrate the need for a low impedance ground plane. Charge needed to turn-on the MOSFET gates comes from the decoupling capacitors CVDD and CB. Current in the low-side gate driver flows from CVDD through the internal driver, into the MOSFET gate and out the Source. The return connection back to the decoupling capacitor is made through the ground plane. Any inductance or resistance in the ground return path causes a voltage spike or ringing to appear on the source of the MOSFET. This voltage works against the gate drive voltage and can either slow down or turn off the MOSFET during the period where it should be turned on. Current in the high-side driver is sourced from capacitor CB and flows into the HB pin and out the HO pin, into the gate of the high side MOSFET. The return path for the current is from the source of the MOSFET and back to capacitor CB. The high-side circuit return path usually does not have a low impedance ground plane so the trace connections in this critical path should be short and wide to minimize parasitic inductance. As with the low-side circuit, impedance between the MOSFET source and the decoupling capacitor causes negative voltage feedback which fights the turn-on of the MOSFET. It is important to note that capacitor CB must be placed close to the HB and HS pins. This capacitor not only provides all the energy for turn-on but it must also keep HB pin noise and ripple low for proper operation of the highside drive circuitry.
Low -side drive turn-on current path
MIC4103/4104 low impedance connections are important during turn-off for the same reasons given in the turn-on explanation. Remember that during turn-off current flowing through the internal diode replenishes charge in the bootstrap capacitor, CB.
Figure 10. Turn-Off Current Paths
The following circuit guidelines should be adhered to for optimum circuit performance: 1. The VDD and HB bypass capacitors must be placed close to the supply and ground pins. It is critical that the trace length between the high side decoupling capacitor (CB) and the HB & HS pins be minimized to reduce trace inductance. 2. A ground plane should be used to minimize parasitic inductance and impedance of the return paths. The MIC4103 is capable of greater than 2A peak currents and any impedance between the MIC4103, the decoupling capacitors, and the external MOSFET will degrade the performance of the driver. 3. Trace out the high di/dt and dv/dt paths, as shown in Figures 9 and 10 and minimize trace length and loop area for these connections. Minimizing these parameters decreases the parasitic inductance and the radiated EMI generated by fast rise and fall times.
Vdd gnd plane CVdd HB
LO
Vss LI
Level shift
HO CB
High-side drive turn-on current path
gnd plane
HS
HI
Figure 9. Turn-On Current Paths
Figure 10 shows the critical current paths when the driver outputs go low and turn off the external MOSFETs. Short, October 2007 14
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CB CVDD HI Vdd
Level shift
MIC4103/4104
Vin
HB HO HS High-Side Fet HS (switch) Node Low-Side Fet Cin
LI
LO
MIC4103 Vss
Figure 11. Synchronous Buck Converter Power Stage
A typical layout of a synchronous Buck converter power stage (Figure 11) is shown in Figure 12. The circuit is configured as a synchronous buck power stage. The high-side MOSFET drain connects to the input supply voltage and the source connects to the switching node. The low-side MOSFET drain connects to the switching node and its source is connected to ground. The buck converter output inductor (not shown) would connect to the switching node. The high-side drive trace, HO, is routed on top of its return trace, HS, to minimize loop area and parasitic inductance. The low-side drive trace LO is routed over the ground plane which minimizes the impedance of that current path. The decoupling capacitors, CB and CVDD are placed to minimize trace length between the capacitors and their respective pins. This close placement is necessary to efficiently charge capacitor CB when the HS node is low. All traces are 0.025" wide or greater to reduce impedance. Cin is used to decouple the high current path through the MOSFETs.
Top Side
Bottom Side
Figure 12. Typical Layout of a Synchronous Buck Converter Power Stage
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Package Information
8-Pin SOIC (M)
(R) 8-Pin MLF (ML)
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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